1. General
The semiconductor industry continually moves toward fabricating larger and more complex functions on a given semiconductor chip. The larger and more complex functions are achieved by reducing device sizes and spacing and by reducing the junction depth of regions formed in the semiconductor substrate. However, strict adherence to design rules is required of layout designs and poses significant necessary obstacles to reducing layout area utilization. Since many integrated circuits include very large numbers of standard cells, any reduction of cell dimensions can yield large benefits in terms of overall circuit density.
2. Description of the Related Art
With reference first to FIG. 1, a first standard cell complementary metal oxide semiconductor (CMOS) device 100 is shown in layout view. Such devices are employed in a variety of integrated circuit applications including non-limiting examples of buffers, inverters and memory units. CMOS device 100 is illustrated as being fabricated in a silicon bulk substrate 101 of p-type conductivity. CMOS device 100 includes P-MOS transistor 120 and N-MOS transistor 130. Power and ground are provided by voltage rails 105 and 106, respectively. P-MOS transistor 120 includes a p-type diffusion structure 121 and N-MOS transistor 130 includes and n-type diffusion structure 131. Though not separately illustrated, the P-MOS transistor 120 further includes a well of n-type conductivity substrate (N-well) wherein the p-type diffusion structure 121 is disposed. Each transistor further includes a gate structure 140, typically polysilicon or a silicided polysilicon, coupled to gate/metal contact 110 for coupling the gate structure 140 to a metal structure (not separately illustrated). Gate structure 140 is electrically common between the two transistors and effects complementary switching of the respective transistors in accordance with the voltage signal applied thereto via contact 110. P-type diffusion structure 121 includes drain diffusion region 123 on one side of the gate structure 140. Similarly, n-type diffusion structure 131 includes drain diffusion region 133 on the same side of the gate structure 140 as drain diffusion region 123 is to p-type diffusion structure 121. Each drain diffusion region 123 and 133 is commonly coupled via respective diffusion/metal contacts 110 to output metal 150. On the opposite side of the gate structure 140 (i.e. across the transistor channels) are source diffusion regions 122 and 132 corresponding to respective channel widths of each of p-type diffusion structure 121 and n-type diffusion structure 131, respectively. Each of P-MOS transistor 120 and N-MOS transistor 130 has a channel width labeled 160 and 170, respectively. Source diffusion structure 121 also includes dogbone diffusion region 125 and interconnect diffusion region 124 running between dogbone diffusion region 125 and source diffusion region 122. Diffusion/metal contact 110 couples source diffusion region 122 to metal 103 via dogbone diffusion region 125 and connecting diffusion region 124. Metal 103 comprises a portion of voltage rail 105. Well pick-up diffusion 107 is a diffusion region of n-type conductivity also disposed within the N-well substrate (not separately illustrated) and is coupled to voltage rail 105 via diffusion/metal contacts 110 which couple well pick-up diffusion 107 to metal 103. Dogbone diffusion region 125 is illustrated butting well pick-up diffusion 107 and having a width W1 and a length L1. Interconnect diffusion region 124 has a length L2 and a width W2. Dogbone diffusion region 125 and interconnect diffusion region 124 have a combined length Lp which is also the separation between well pick-up diffusion 107 and source diffusion region 122.
Similarly, source diffusion structure 131 also includes dogbone diffusion region 135 and interconnect diffusion region 134 running between dogbone diffusion region 135 and source diffusion region 132. Diffusion/metal contact 110 couples source diffusion region 132 to metal 104 via dogbone diffusion region 135 and connecting diffusion region 134. Metal 104 comprises a portion of voltage rail 106. Bulk substrate pick-up diffusion 108 is a diffusion region of p-type conductivity and is coupled to voltage rail 106 via diffusion/metal contacts 110 which couple bulk substrate pick-up diffusion 108 to metal 104. Dogbone diffusion region 135 is illustrated butting bulk substrate pick-up diffusion 108 and having a width W3 and a length L3. Interconnect diffusion region 134 has a length L4 and a width W4. Dogbone diffusion region 135 and interconnect diffusion region 134 have a combined length Ln which is also the separation between bulk substrate pick-up diffusion 108 and source diffusion region 132.
As can be appreciated by examination of the layout exhibited in FIG. 1, significant area is dedicated to the coupling of the source diffusion regions to the voltage rails. Some of the design considerations which dictate the overall spacing Lp include minimum contact to diffusion spacing, minimum contact overlap of diffusion, minimum contact spacing, minimum active overlap of polysilicon, minimum contact size, minimum source diffusion to dogbone diffusion spacing.
Turning now to FIG. 2, a second standard cell CMOS device 200 is shown in layout view and is fabricated in a silicon bulk substrate 201 of p-type conductivity. CMOS device 200 includes P-MOS transistor 220 and N-MOS transistor 230. Power and ground are provided by voltage rails 205 and 206, respectively. P-MOS transistor 220 includes a p-type diffusion structure 221 and N-MOS transistor 230 includes and n-type diffusion structure 231. Though not separately illustrated, the P-MOS transistor 220 further includes a well of n-type conductivity substrate (N-well) wherein the p-type diffusion structure 221 is disposed. Each transistor further includes a gate structure 240 coupled to gate/metal contact 210 for coupling the gate structure 240 to a metal structure (not separately illustrated). Gate structure 240 is electrically common between the two transistors and effects complementary switching of the respective transistors in accordance with the voltage signal applied thereto via contact 210. P-type diffusion structure 221 includes drain diffusion region 223 on one side of the gate structure 240. Similarly, n-type diffusion structure 231 includes drain diffusion region 233 on the same side of the gate structure 240 as drain diffusion region 223 is to p-type diffusion structure 221. Each drain diffusion region 223 and 233 is commonly coupled via respective diffusion/metal contacts 210 to output metal 250. On the opposite side of the gate structure 240 (i.e. across the transistor channels) are source diffusion regions 222 and 232 corresponding to respective channel widths of each of p-type diffusion structure 221 and n-type diffusion structure 231, respectively. Each of P-MOS transistor 220 and N-MOS transistor 230 has a channel width labeled 260 and 270, respectively. Source diffusion structure 221 also includes dogbone diffusion region 225 and interconnect diffusion region 224 running between dogbone diffusion region 225 and source diffusion region 222. Metal 203 comprises a portion of voltage rail 205. Well pick-up diffusion 207 is a diffusion region of n-type conductivity also disposed within the N-well substrate (not separately illustrated) and is coupled to voltage rail 205. Dogbone diffusion region 225 is butting well pick-up diffusion 207 and having a width W1′ and a length L1′. Interconnect diffusion region 224 has a length L2′ and a width W2′. Dogbone diffusion region 225 and interconnect diffusion region 224 have a combined length Lp′ which is also the separation between well pick-up diffusion 207 and source diffusion region 222. Silicided source diffusion region 222, including silicided interconnect diffusion region and silicided dogbone diffusion region 225, and a silicided well pick-up diffusion 207 provides ohmic coupling between the source and well pick-up. In turn, contacts 210, which are preferably silicide/metal contacts but which may take the form of diffusion/metal contacts, ohmically couple the pick-up diffusion 207 to metal 203, thereby providing ohmic coupling of the source region 222 to voltage rail 205.
Similarly, source diffusion structure 231 also includes dogbone diffusion region 235 and interconnect diffusion region 234 running between dogbone diffusion region 235 and source diffusion region 232. Metal 204 comprises a portion of voltage rail 206. Bulk substrate pick-up diffusion 208 is a diffusion region of p-type conductivity and is coupled to voltage rail 206. Dogbone diffusion region 235 is illustrated butting bulk substrate pick-up diffusion 208 and having a width W3′ and a length L3′. Interconnect diffusion region 234 has a length L4′ and a width W4′. Dogbone diffusion region 235 and interconnect diffusion region 234 have a combined length Ln′ which is also the separation between bulk substrate pick-up diffusion 208 and source diffusion region 232. Silicided source diffusion region 232, including silicided interconnect diffusion region and silicided dogbone diffusion region 235, and a silicided well pick-up diffusion 208 provides ohmic coupling between the source and well pick-up. In turn, contacts 210, which are preferably silicide/metal contacts but which may take the form of diffusion/metal contacts, ohmically couple the pick-up diffusion 208 to metal 204, thereby providing ohmic coupling of the source region 232 to voltage rail 206.
As can be appreciated by examination of the layout exhibited in FIG. 2, though some improvements over the layout exhibited in FIG. 1 are apparent, significant area is still dedicated to the coupling of the source diffusion regions to the voltage rails. Some of the design considerations which dictate the overall spacing Lp′ include minimum contact to diffusion spacing, minimum contact overlap of diffusion, minimum active overlap of polysilicon, minimum source diffusion to dogbone diffusion spacing.